View WEDPY256K72V-150BM_652127.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

White Electronic Designs
256Kx72 Synchronous Pipeline SRAM
FEATURES
Fast clock speed: 100, 133, 150, 166 and 200** MHz Fast access time: 5.0, 4.0, 3.8, 3.5, 3.1ns +3.3V power supply (VCC) +2.5V output buffer supply (VCCQ) Single-cycle deselect Common data inputs and data outputs Clock-controlled and registered addresses, data I/Os and control signals SNOOZE MODE for reduced-power standby Individual BYTE WRITE control and GLOBAL WRITE Six chip enables for simple depth expansion and address pipeline Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Packaging: 159-bump PBGA package, 14mm x 22mm Commercial, industrial, and military temperature ranges User configurable as 512K x 36, or 1M x 18
**200 MHz for commercial and industrial temperature only.
SA0-17 ADSC# ADSP# ADV# BWa# BWb# BWc# BWd# BWE# CS11# CS21# CS21 CLK GW# MODE OE1# ZZ
WEDPY256K72V-XBX
DESCRIPTION
The WEDPY256K72V-XBX employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs into a single PBGA package to provide 256K x 72 configuration. All synchronous inputs are controlled by a positive-edgetriggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, and active LOW chip selects (CS#). Asynchronous inputs include the output enable (OE1#/OE2#), clock (CLK).
* This product is subject to change without notice.
FIGURE 1 - BLOCK DIAGRAM
256Kx36 A0-17 SSRAM ADSC# ADSP# ADV# BWa# BWb# BWc# BWd# WE# DQ0-35 CS1# CS2# CS2 CLK GW# MODE OE# ZZ
IC1
DQ0-35
BWe# BWf# BWg# BWh# CS11# CS22# CS22
OE2#
256Kx36 SSRAM A0-17 ADSC# ADSP# ADV# BWa# BWb# BWc# BWd# WE# CS1# CS2# CS2 CLK GW# MODE OE# ZZ
IC2
DQ36-71
August 2004 Rev. 7
1
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PIN CONFIGURATION
(Top View) 1 A B C D E F G H J K L M N P R T -- ADV# OE1# CS21# BWc# CS21 CS11# DQ26 SA17 SA16 SA14 SA15 OE2# BWE# BWh# CS12# 2 DQ16 DQ17 ADSP# CLK BWb# DQ18 DQ19 DQ20 DQ21 DQ52 DQ51 DQ53 ADSC# CS22# BWg# CS22 3 DQ14 DQ15 GW# BWa# BWd# DQ22 DQ23 DQ24 DQ25 DQ49 DQ50 DQ48 DQ47 DQ46 BWf# DQ62 4 DQ12 DQ11 DQ13 GND GND VCC GND VCCQ VCC GND VCC GND VCCQ DQ45 BWe# DQ54 5 DQ10 DQ9 DNU GND VCC VCCQ VCC VCCQ VCC VCCQ GND GND VCC GND DQ56 DQ55 6 ZZ DQ7 GND VCC GND GND VCCQ VCC VCCQ VCC VCCQ VCC GND DNU DQ60 DQ57 7
WEDPY256K72V-XBX
8 DQ4 DQ3 DQ2 SA11 SA8 DQ30 DQ31 DQ28 DQ27 DQ40 DQ42 DQ43 MODE DQ64 DQ65 DQ63
9 DQO DQ1 SA12 SA9 SA7 DQ34 DQ33 DQ32 DQ39 DQ38 DQ41 SA3 SA2 DQ66 DQ69 DQ67
10 DQ8 SA13 SA10 SA6 SAO SA1 SA5 DQ35 DQ37 DQ36 DQ44 DNU SA4 DQ70 DQ71 DQ68
DQ6 DQ5 DQ29 VCCQ GND VCC GND VCC VCCQ GND VCC GND GND DQ59 DQ61 DQ58
DNU = DO NOT USE. RESERVED FOR FUTURE UPGRADES.
August 2004 Rev. 7
2
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WEDPY256K72V-XBX
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
First Address (External) X...X00 X...X01 X...X10 X...X11 Second Address (Internal) X...X01 X...X00 X...X11 X...X10 Third Address (Internal) X...X10 X...X11 X...X00 X...X01 Fourth Address (Internal) X...X11 X...X10 X...X01 X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
First Address (External) X...X00 X...X01 X...X10 X...X11 Second Address (Internal) X...X01 X...X10 X...X11 X...X00 Third Address (Internal) X...X10 X...X11 X...X00 X...X01 Fourth Address (Internal) X...X11 X...X00 X...X01 X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (X36)
Function READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes GW# H H H H L BWE# H L L L X BWa# X H L L X BWb# X H H L X BWc# X H H L X BWd# X H H L X
NOTE: 1. Using BWE# and BWa# through BWd#, any one or more bytes may be written. 2. Insert BWe# through BWh# for DQ36-71 control.
August 2004 Rev. 7
3
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
TRUTH TABLE
Operation Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CS1 H L L L L X L L L L L X X H H X H X X H H X H CS2 X X H X H X L L L L L X X X X X X X X X X X X CS2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H
WEDPY256K72V-XBX
ADV X X X X X X X X X X X L L L L L L H H H H H H
WRITE X X X X X X X X L H H H H H H L L H H H H L L
OE X X X X X X L H X L H L H L H X X L H L H X X
CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H H L-H L-H L-H
DQ HIGH Z HIGH Z HIGH Z HIGH Z HIGH Z HIGH Z Q HIGH Z D Q HIGH Z Q HIGH Z Q HIGH Z D D Q HIGH Z Q HIGH Z D D
NOTE: 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or WE#) are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# High. 3. BWa enables WRITEs to DQ0-8. BWb# enables WRITEs to DQ9-17. BWc enables WRITEs to DQ18-26. BWd# enables WRITE to DQ27-35. 4. All inputs excepts OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending bursts. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be held in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
August 2004 Rev. 7
4
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply relative to VSS Voltage on VCCQ Supply relative to VSS VIN (DQx) VIN (Inputs) Storage Temperature (BGA) Short Circuit Output Current -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCCQ +0.5V -0.5V to VCC +0.5V -55C to +150C 100 mA
WEDPY256K72V-XBX
* Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
-55C TA +125C Description Input High (Logic 1)Voltage Input Low (Logic 0) Voltage Input Leakage Current Ouptut Leakage Current Output High Voltage Output Low Voltage Supply Voltage Output Buffer Supply Symbol VIH VIHQ VIL ILI ILO VOH VOL VCC VCCQ Conditions Inputs Data (DQ) 0V VIN VCC Outputs disabled, 0V VIN VCCQ (DQX) IOH = -1.0mA IOL = 1.0mA Min 1.7 1.7 -0.3 -2.0 -1.0 2.0 -- 3.135 2.375 Max VCC +0.3 VCCQ +0.3 0.7 2.0 1.0 -- 0.4 3.6 2.9 Units V V V A A V V V V Notes 1 1 1 2 1 1 1 1
NOTES: 1. All voltages referenced to Vss (GND).
DC CHARACTERISTICS
-55C TA +125C Description
Power Supply Current: Operating CMOS Standby Clock Running IDD ISB2 ISB4
Conditions
Device selected; All inputs VIL or VIH; Cycle time tKC MIN; VCC = MAX; Outputs open Device deselected; VCC = MAX; All inputs Vss + 0.2 Device deselected; VCC = MAX; All inputs Vss + 0.2 or VCC -0.2; Cycle time tKC MIN; ADSC#, ADSP#, GW#, BWx#, ADV#, VIH
100 MHz 133 MHz 150 MHz 160 MHz 200 MHz
600 20 170 750 20 180 950 20 220 950 20 220 1050 20 240
Units
mA mA mA
Notes
1.2 2 2
NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode).
BGA CAPACITANCE
TA = +25C, F = 1MHz Description Control Input Capacitance Common Control Input Capacitance (2) Input/Output Capacitance (DQ) Address Capacitance (SA) Clock Capacitance (CLK) Symbol Max Units Notes CI 6 pF 1 CIC 15 pF 1 CO 10 pF 1 CsA 15 pF 1 CCK 12 pF 1
BGA THERMAL RESISTANCE
Description Junction to Ambient (No Airflow) Junction to Ball Junction to Case (Top) Symbol Max Theta JA 30.5 Theta JB 17.3 Theta JC 9.8 Units Notes 0 C/W 1 0 C/W 1 0 C/W 1
NOTE 1: Refer to BGA Thermal Resistance Correlation application note at www.wedc. com in the application notes section for modeling conditions.
NOTES: 1. This parameter is guaranteed by design but not tested. 2. Common Inputs = zz, ADV#, ADSP#, GW#, ADSC#, MODE#, BWE#.
August 2004 Rev. 7
5
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC CHARACTERISTICS
-55C TA +125C
Symbol Parameter Clock Clock Cycle Time Clock Frequency Clock HIGH Time (6) Clock LOW Time (6) Output Times Clock to output valid Clock to output invalid (2) Clock to output on Low-Z (2,3,4) Clock to output in High-Z (2,3,4) OE# to output valid (5) OE# to output in Low-Z (2,3,4) OE# to output in High Z (2,3,4) Setup Time Address (6,7) Write Enable (WE#) (7) Address status, (ADSC#, ADSP#) (7) Address advance (ADV#) (7) Data-in (6,7) Chip enable (CE#) (7) Hold Times Address (7) (7) Address status (ADSC#, ADSP#) (7) Address advance (ADV) (7) Write Enable (WE#) (7) Data-in (6,7) Chip Enable (CS) (7) tKC tKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tAS tWS tADSS tAAS tDS tCES tAH tADSH tAAH tWH tDH tCEH 100MHz Min. Max 10 100 3.0 3.0 5.0 1.5 1.5 5.0 5.0 0 4.5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0 4.2 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 1.5 0 4.2 4.2 0 2.5 2.5 4.0 1.5 0 133MHz Min Max 7.5 133 2.5 2.5
WEDPY256K72V-XBX
150MHz Min Max 7.0 150
166MHz Min Max 6.0 166 2.3 2.3
200MHz* Min Max 5.0 200 2.0 2.0
Units ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3.8 15 0 4.0 4.0 0 4.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5
3.5 1.0 0 3.5 3.5 0 3.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5
3.1
3.1 3.1 3.0
* Commercial and industrial temperatures only. NOTES: 1. Test conditions as specified with the output loading as shown in test conditions unless otherwise noted. 2. This parameter is measured with output load as shown in test conditions. 3. This parameter is not tested. 4. Transition is measured 500mV from steady state voltage. 5. OE# is a "Don't Care" when a byte write enable is sampled LOW. 6. Measured at HIGH above VIH and LOW below VIL 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK to remain enabled.
Output Loads
Output Z0 = 50
+2.5V
AC Test Conditions
Parameter Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load 2.5V I/O Unit Vss to 2.5 V 1 ns 1.25 V 1.25 V See figures, at left
1,667
50
Output 1,538 5pF
Vt = 1.25V for 2.5 V I/O
Vt = 1.25V
AC Output Load Equivalent
August 2004 Rev. 7 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and a ignored.
WEDPY256K72V-XBX
ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tzz is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current
NOTES: 1. This parameter is sampled.
Conditions ZZ VIH
Symbol ISB2Z tZZ tRZZ tZZI tRZZI
Min
Max 20 2 (tKC)
Units mA ns ns
Notes
1 1 1 1
2 (tKC) 2 (tKC) 0
ns ns
SNOOZE MODE WAVEFORM
CLOCK
tZZ
ZZ
tRZZ
tZZI
ISUPPLY
tRZZI
IISB2Z
ALL INPUTS (except ZZ)
Deselect or Read Only
DESELECT or READ Only
Normal Operation Cycle
Output (Q) HIGH-Z
DON'T CARE
August 2004 Rev. 7
7
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIGURE 2 - READ TIMING3
WEDPY256K72V-XBX
tKC CLK tKH tKL tADSS tADSH ADSP# tADSS tADSH ADSC# tAS tAH Address A1 tWS tWH GW#, BWE# BWa-BWd tCES tCEH CS1# (Note 2) tAAS tAAH ADV#
ADV# suspends burst Deselect cycle (Note 4)
A2
A3 Burst continued with new base address
OE# (NOTE 3) tKQLZ Q# High-Z tKQ Single READ Burst Read Cycle Don't care Undefined tOEHZ Q(A1) tOEQ tOELZ tKQ tKQX Q(A2) (NOTE 1) Q
(A2+1)
tKQHZ
Q(A3)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Burst wraps around to its initial state
NOTES: 1. DQ (A2) refers to output from address A2. DQ (A2+ 1) refers to output from the next internal burst address following A2. 2. CS2# and CS2# have timing identical to CS1#. On this diagram. When CS1 is LOW, CS2# is LOW and CS2# is HIGH. When CS1# is HIGH, CS2# is HIGH and CS2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect.
August 2004 Rev. 7
8
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIGURE 3 - WRITE TIMING
WEDPY256K72V-XBX
tKC CLK tKH tADSS tADSH ADSP# tADSS tADSH ADSC# tAS tAH Address A1 A2
Byte write signals are ignored for first cycle when ADSP# initiates burst. ADSC# extends burst
tKL
tADSS tADSH
A3
tWS tWH
BWE# BWa-BWd# (Note 5) tWS tWH GW# tCES tCEH CS1# (Note 2) tAAS tAAH ADV# (Note 4)
ADV# suspends burst
OE#
(Note 3) tDS
D tQEHZ Q
Burst Read Cycle
D(A1)
D(A1)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
(Note 1)
Single Write
Burst Write Cycle
Extended Burst Write
Don't care
Undefined
NOTES: 1. D(A2) refers to input for address A2. D(A2 +1) refers to input for the next internal burst address following A2. 2. CS2# and CS2 have timing identical to CS1#. On this diagram, when CS1# is LOW, CS2# is LOW and CS2# is HIGH. When CS1# is HIGH, CS2 is HIGH and CS2 is LOW. 3. OE# msut be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contentinon for th etime period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH, BWE# LOW and BWa#-BWd# LOW.
August 2004 Rev. 7
9
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIGURE 5 - READ/WRITE TIMING3
WEDPY256K72V-XBX
tKC
CLK tKH tKL tADSS tADSH ADSP#
ADSC# tAS Address A1 A2 tAH A3 A4
A5 A6
BWE#, BWa#-BWd# (Note 4)
tWS tWH
tCES tCEH CS# (Note 2)
ADV#
OE# tKQ D High-Z tKQLZ Q# High-Z Q(A1) tOEHZ Q(A2) tDS tDH D(A2) tOELZ
D(A5) D(A6)
(NOTE 1) Q(A4) Q
(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs (Note 5)
Single WRITE
Burst Read
Back-to-Back WRITEs
Don't care
Undefined
NOTES: 1. Q(A4) refers to output from addrss A4. Q(A4 + 1) refers to output from the next internal burst address to following A4. 2. CS2# and CS2 have timing identical to CS1#. On this diagram, when CS1# is LOW, CS2# is LOW and CS2# is HIGH. When CS1# is HIGH, CS2 is HIGH and CS2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to back READs may be controlled by either ADSP# or ADSC#.
August 2004 Rev. 7
10
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WEDPY256K72V-XBX
PACKAGE DIMENSION - 159 BUMP PBGA Bottom View
159x ? 0.762 (0.030) NOM
19.05 (0.750) NOM 1.27 (0.050) NOM
22.1 (0.870) MAX
1.27 (0.050) NOM 11.43 (0.450) NOM 14.1 (0.555) MAX
0.61 (0.024) NOM
2.03 (0.080) MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P Y 256K72 V - X B X
DEVICE GRADE: M = Military I = Industrial -55C to +125C -40C to +85C 0C to +70C
C = Commercial PACKAGE:
B = 159 Plastic Ball Grid Array (PBGA) FREQUENCY (MHz) 100 = 100MHz 133 = 133MHz 150 = 150MHz 166 = 166MHz 200 = 200MHZ 3.3V Power Supply CONFIGURATION, 256k x 72 SSRAM, Pipeline Burst PLASTIC WHITE ELECTRONIC DESIGNS CORP.
August 2004 Rev. 7 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
256K x 72 Synchronous SRAM
WEDPY256K72V-XBX
Revision History Rev #
Rev 0 Rev 1
History
Initial Release Changes (Pg. 1, 5) 1.1 Add speed grades (100MHz-200MHz) to DC Characteristics Table Change (Pg. 1) 1.1 Change product status from Advanced to Preliminary.
Release Date
July 2001
Status
Advanced
Rev 2
January 2002
Preliminary
Rev 3
Change (Pg. 1, 11) 1.1 Change Package Dimension title from Top View to Bottom View
September 2002
Preliminary
Rev 4
Changes (Pg. 1, 5) 1.1 BGA Capacitance: Change CI from 10pF to 6pF 1.2 Change CIP to CIC, capacitance from 20pF to 15pF 1.3 Change CCK from 20pF to 12pF 1.4 Change CO from 12pF to 10pF 1.5 Change CSA from 20pF to 15pF 1.6 Add Note 2: Control Inputs = zz, ADV#, ADSP#, GW#, ADSC#, MODE#, BWE#.
November 2002
Preliminary
Rev 5
Changes (Pg. 1, 5, 7, 12) 1.1 Add Thermal Resistance Table 1.2 Correct formatting on page 7
May 2003
Preliminary
Rev 6
Changes (Pg. 1, 11, 12) 1.1 Change mechanical drawing to new style
November 2003
Preliminary
Rev 7
Changes (Pg. 1, 12 1.1 Change status to Final
August 2004
Final
August 2004 Rev. 7
12
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

▲Up To Search▲

Price & Availability of WEDPY256K72V-150BM

	To Download WEDPY256K72V-150BM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .